Integrated circuits (ICs) may be damaged by electrostatic discharge (ESD) phenomena. An IC may be exposed to ESD from many sources. The major source of ESD exposure to ICs is from human bodies, and is known as the Human Body Model (HBM) ESD source. A charge of about 0.6 .mu.C can be induced on a body capacitance of 150 pF, leading to electrostatic potentials of 4 kV or greater. Contact with a charged human body by an uncharged or grounded IC pin can result in a discharge for about 100 nS with peak currents of several amperes.
A second source of ESD is from metallic objects, and is known as the machine model (MM) ESD source. The MM ESD source is characterized by a greater capacitance and lower internal resistance than the HBM ESD source. The MM ESD model can result in ESD transients with significantly higher rise times than the HBM ESD source.
A third ESD model is the charged device model (CDM). Unlike the HBM ESD source and the MM ESD source, the CDM ESD source includes situations where the IC itself is charged and discharges to ground. Thus, the ESD discharge current flows in the opposite direction than that of the HBM ESD source and the MM ESD source. CDM pulses also have very fast rise times compared to the HEM ESD source.
The most common protection schemes used in metal oxide semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with a n-type metal oxide semiconductor (nMOS) device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be set by varying the NMOS device width from the drain to the source under the gate oxide. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that nMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism found in the nMOS protection device operating as a parasitic bipolar transistor in snapback conditions is the onset of second breakdown. Second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self heating. The peak nMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
In MOS ICs that employ thick gate oxide designs, the protection provided by nMOS protection devices operating in snapback conditions is generally adequate. Nevertheless, the trend with modern devices is for a decrease in thickness of the gate oxide layer. As the gate oxide layer thickness decreases, the parasitic bipolar transistor protection provided by a nMOS device may fail to provide adequate protection to the gate oxide layer. This may result in ESD protection devices that may be damaged by an ESD pulse.